The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to design and manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling alone has not been sufficient to achieve at least some performance goals.
As one example, non-volatile memories have become a critical component of IC designs. One type of non-volatile memory includes a read-only memory (ROM), such as a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or FLASH memory, among others. In various cases, a ROM may be mapped to look up tables (LUTs) or to dedicated random-access memory blocks (BRAMs). However, using LUTs comes at a cost of using logic cells needed to implement logic circuits, thus LUTs are generally used for smaller memories. BRAMS, on the other hand, may generally be used to instantiate large, registered ROMs. With respect to ROM performance, if a ROM drives an arithmetic operator, or if a ROM address is driven by an arithmetic operator, performance (e.g., maximum operating frequency (FMax)) may be degraded. Also, and in some cases, the amount of IC area occupied by such ROM and arithmetic operator structures may present additional design and/or performance challenges.
Accordingly, there is a need for improved systems providing optimization of read-only memory.